Dual-leadframe Multi-chip Package

ABSTRACT

A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Patent Application is a Divisional Application of a co-pendingapplication Ser. No. 13/411,990 with attorney Docket# APOM040D1 andfiled on Mar. 5, 2012. Thus, this application claims the Priority Dateof the co-pending application Ser. No. 13/411,990. Also, the Disclosuresmade in the co-pending application Ser. No. 13/411,990 are herebyincorporated by reference.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of a pending US patentapplication entitled “Dual-leadframe Multi-chip Package and Method ofManufacture” by Kai Liu et al with filing date of Mar. 29, 2010 andapplication Ser. No. 12/749,505 whose content is hereby incorporated byreference for all purposes.

FIELD OF THE INVENTION

This invention relates to a semiconductor packaging structure and itsmanufacturing method, and more specifically to a dual-leadframemulti-chip package and its manufacturing method.

BACKGROUND OF THE INVENTION

A power metal-oxide-semiconductor field effect transistor (MOSFET)device, featuring high integration density, high reliability, extremelylow static current leakage and improving power handling capacity, iswidely applied in consumer electronics, computers and other relatedsectors.

In the existing art, as shown in FIG. 1, when co-packaging a high-sidemetal-oxide-semiconductor field effect transistor (HS MOSFET) 2 and alow-side metal-oxide-semiconductor field effect transistor (LS MOSFET)1, the HS MOSFET 2 and LS MOSFET 1 are installed on die pad 4 and diepad 3 of a leadframe respectively, and the connections from the topelectrodes of LS MOSFET 1 and HS MOSFET 2 to the pins of the die pad, aswell as the connection between the top source contact area of the HSMOSFET 2 and the bottom drain contact area of LS MOSFET 1 are realizedthrough bond wires 5.

In the existing art, as shown in FIG. 2, a surface mounted capacitor 11may be configured on the surface of the semiconductor package 12 todecrease parasitic inductance.

In the package of the abovementioned device, with the chips connected bybond wires, the resistance and inductance between the chips areincreased; and with the capacitor mounted on semiconductor surface, thesize and cost of the semiconductor package are also increased.

SUMMARY OF THE INVENTION

The present invention aims at providing a dual-leadframe multi-chippackage and its manufacturing method, wherein its packaging structurerealizes a connection between chips and between leadframes throughconnecting plates, thus to decrease the resistance and inductancebetween the chips, integrate a bypass capacitor in package, reduce theparasitic inductance during packaging, improve the energy conversionefficiency of the whole device and reduce the sizes of semiconductorpackage. The present invention also boasts a simple process, easyoperation and low manufacturing cost.

To achieve the above purpose, the present invention adopts the followingtechnical solution: a dual-leadframe multi-chip package, characterizedin that, comprising:

Two leadframes, namely a first leadframe and a second leadframe, whereinthe first leadframe comprises a die pad and multiple outer pins, thesecond leadframe comprises a second die padtie bar;

Multiple chips, each having a plurality of top contact areas and abottom contact area; wherein the multiple chips comprise a first chipand a second chip; the first chip is mounted on the first die pad, thesecond chip is mounted on the second die pad; the bottom contact area ofthe first chip is connected with the first die pad, the bottom contactarea of the second chip is connected with second die pad;

a plurality of connecting plates, used for the connection in multi-chippackage, which comprise a three-dimensional connecting plate and a topconnecting plate, wherein the three-dimensional connecting plate and thesecond die pad form an integrated body, or the three-dimensionalconnecting plate is electrically connected with the second die pad, andthe three-dimensional connecting plate connects a top contact area ofthe first chip so that the first chip is electrically connected with thesecond die pad, thus the first chip is electrically connected with thesecond chip; the top connecting plate connects a top contact area of thesecond chip and an outer pin of the first leadframe.

The abovementioned dual-leadframe multi-chip package, characterized inthat, the first chip is a high-side metal-oxide-semiconductor fieldeffect transistor, and the second chip is a low-sidemetal-oxide-semiconductor field effect transistor.

A dual-leadframe multi-chip package, characterized in that, comprising:

Two leadframes, namely a first leadframe and a second leadframerespectively, wherein the first leadframe comprises a first die pad andmultiple outer pins, the second leadframe comprises a second die padtiebar;

Multiple chips, each having a top contact area and a bottom contact arearespectively; wherein the multiple chips further comprise a first chip,a second chip and a third chip; the first chip and the third chip aremounted on the first die pad, the second chip is mounted on the seconddie pad, the bottom contact areas of the third chip and the first chipare electrically connected with the first die pad respectively, thebottom contact area of the second chip is electrically connected withthe second die pad, the first chip and the second chip each furthercomprises a top gate contact area respectively, the gate contact areasof the first chip and the second chip are connected with the outer pinsof the first leadframe respectively and are different from the topcontact areas;

A top connecting plate, used for the connection in multi-chip package,wherein the top connecting plate connects the top contact area of thesecond chip and an outer pin of the first leadframe, and connects thetop contact area of the third chip at the same time;

The top contact area of the first chip is electrically connected withthe second die pad.

The said dual-leadframe multi-chip package, characterized in that,further comprising a three-dimensional connecting plate, wherein thethree-dimensional connecting plate and the second die pad form anintegrated body, or the three-dimensional connecting plate iselectrically connected with the second die pad, and thethree-dimensional connecting plate connects the top contact area of thefirst chip so that the top contact area of the first chip iselectrically connected with the second die pad.

The said dual-leadframe multi-chip package, characterized in that, thetop contact area of the first chip is connected with the second die padthrough bond wires.

The said dual-leadframe multi-chip package, characterized in that, thefirst chip and the third chip are integrated to form a chip mounted onthe first die pad.

The said dual-leadframe multi-chip package, characterized in that, thefirst chip is a high-side metal-oxide-semiconductor field effecttransistor, the second chip is a low-side metal-oxide-semiconductorfield effect transistor and the third chip is bypass capacitor.

The said dual-leadframe multi-chip package, characterized in that, theconnecting plate further comprises multiple holes, wherein the holes areused for adsorbing bonding materials so that the connecting plate isstably connected with the top contact area of the chip.

The said dual-leadframe multi-chip package, characterized in that, thegate contact areas of the first chip and the second chip are connectedwith the outer pins of the first leadframe respectively.

A method for manufacturing dual-leadframe multi-chip package,characterized in that, including the following steps:

Step 1: provide a first leadframe, wherein the first leadframe comprisesa first die pad and multiple outer pins;

Step 2: provide multiple chips, comprising a first chip and a secondchip, wherein the first chip and the second chip each comprise a bottomcontact area and a plurality of top contact areas respectively;

Step 3: the first chip is mounted on the first die pad, the bottomcontact area of the first chip is electrically connected with the firstdie pad through bonding materials, preferably, through conductiveadhesive or soldering paste as bonding materials.

Step 4: provide a second leadframe and a three-dimensional connectingplate, wherein the second leadframe comprises a second die padtie bar,the second die pad and the three-dimensional connecting plate form anintegrated body, or the three-dimensional connecting plate iselectrically connected with the second die pad, and thethree-dimensional connecting plate connects a top contact area of thefirst chip;

Step 5: the second chip is mounted on the second die pad, and the bottomcontact area of the second chip is electrically connected with thesecond die pad.

Step 6: provide a top connecting plate, wherein the top connecting plateconnects a top contact area of the second chip and an outer pin of thefirst leadframe.

A method for manufacturing the dual-leadframe multi-chip package,characterized in that, comprising the following steps:

Step 1: provide a first leadframe, wherein the first leadframe comprisesa first die pad and multiple outer pins;

Step 2: provide multiple chips, comprising a first chip, a second chipand a third chip, wherein the first chip and the third chip are mountedon the first die pad, the multiple chips comprises the bottom contactarea and the top contact respectively, the bottom contact areas of thethird chip and the first chip are electrically connected with the firstdie pad;

Step 3: provide a second leadframe, wherein the second leadframecomprises a second die padtie bar, the top contact area of the firstchip connects the second die pad;

Step 4: the second chip is mounted on the second die pad, and the secondchip is electrically connected with the second die pad;

Step 5: provide a top connecting plate, connect the top connecting plateto the top contact area of the second chip and an outer pin of the firstleadframe, and the top connecting plate connects the top contact area ofthe third chip as well;

Step 6: the top contact areas of the first chip and the second chip eachfurther comprise a top gate contact area different from the top contactarea, wherein the gate contact areas of the first chip and the secondchip are each connected with an outer pin of the first leadframerespectively;

Step 7: clean leadframes, adopt plastic package to enclose the die pads,connecting plates and chips, only part of outer pins of the leadframesare exposed, and the pins are electroplated.

A method for manufacturing dual-leadframe multi-chip package,characterized in that, in step 3, further comprising a three-dimensionalconnecting plate, preferably, the three-dimensional connecting plate andthe second die pad form an integrated structure, or thethree-dimensional connecting plate is electrically connected with thesecond die pad, and the three-dimensional connecting plate connects thetop contact area of the first chip, so that the top contact area of thefirst chip is electrically connected with the second die pad.

The method for manufacturing the dual-leadframe multi-chip package,characterized in that, in step 3, further comprising multiple bondwires, wherein the top contact area of the chip is connected with thesecond die pad through the bond wires.

The method for manufacturing the dual-leadframe multi-chip package,characterized in that, in step 2, the first chip and the third chip areintegrated into an integrated chip first, and then the integrated chipis mounted on the first die pad.

The method for manufacturing the dual-leadframe multi-chip package,characterized in that, in Step 6, further comprising the followingsteps:

-   -   a) A solder bump is formed on each of the gates of the first and        second chips;    -   b) The gate contact areas on the first chip and the second chip        are respectively connected with the outer pins of the first        leadframe;

The method for manufacturing the said dual-leadframe multi-chip package,characterized in that, the chips are mounted on the die pads throughbonding materials, and the connecting plates are connected with the topcontact areas of the chips through the bonding materials.

The method for manufacturing the said dual-leadframe multi-chip package,characterized in that, multiple holes are set on the three-dimensionalconnecting plate and top connecting plate, so that the connecting plateis stably connected with the top contact area of the chip through themultiple holes adsorbing and bonding materials.

The method for manufacturing the said dual-leadframe multi-chip package,characterized in that, the first chip is a high-sidemetal-oxide-semiconductor field effect transistor, the second chip is alow-side metal-oxide-semiconductor field effect transistor and the thirdchip is a bypass capacitor.

The method for manufacturing the said dual-leadframe multi-chip package,characterized in that, the first leadframe and the second leadframe forman integrated body.

Comparing with the existing art, a dual-leadframe multi-chip package andits manufacturing method for the present invention have the followingadvantages and favorable effects due to the adoption of theabovementioned technical solution:

-   -   1 1. The present invention simplifies manufacturing process        through a connecting plate connects two chips and the pins of        leadframes simultaneously.    -   2. The present invention decreases the resistance and inductance        between chips, and shortens the distance between the chips since        the connections between the chips and between the chips and the        leadframe are realized via connecting plate.    -   3. The present invention minimizes parasitic inductance and        improves the energy conversion efficiency of the whole device        since a bypass capacitor is integrated in the package of chips.    -   4. The manufacturing of the dual-leadframe multi-chip package        for the present invention boasts simple process, easy operation        and low manufacturing cost.

BRIEF DESCRIPTION OF THE DRAWINGS

Refer to the drawings attached for further description of theembodiments of the present invention. However, the drawings are forexplanation and clarification only and do not constitute the limit ofthe invention's scope.

FIG. 1 is the schematic view of the packaging structure of HS MOSFET andLS MOSET in the existing art.

FIG. 2 is the schematic view of the structure with capacitor mounted onthe semiconductor package surface in the existing art.

FIG. 3 is the schematic view of the structure of the dual-leadframemulti-chip package in Embodiment 1.

FIG. 4 is the flow chart of the method for the manufacturingdual-leadframe multi-chip package in Embodiment 1.

FIG. 5 is the schematic view of the structure of the dual-leadframemulti-chip package in Embodiment 2.

FIG. 6 is the flow chart of the method for manufacturing thedual-leadframe multi-chip package in Embodiment 2.

FIG. 7 is the schematic view of the structure of the first leadframeprovided in the method for manufacturing the dual-leadframe multi-chippackage in Embodiment 2.

FIG. 8 is the schematic view of the structure that the first chip andthe third chip are mounted on the first die pad provided in the methodfor manufacturing the dual-leadframe multi-chip package in Embodiment 2.

FIG. 9 is the schematic view of the structure that the integrated seconddie pad and three-dimensional connecting plate in the method formanufacturing the dual-leadframe multi-chip package in Embodiment 2.

FIG. 10 is the schematic view of the structure of a second chip and topconnecting plate in the method for manufacturing the dual-leadframemulti-chip package in Embodiment 2.

FIG. 11 is the schematic view of the structure of the dual-leadframemulti-chip package in Embodiment 3.

FIG. 12 is the schematic view of the structure of the dual-leadframemulti-chip package in Embodiment 4.

FIG. 13 is the flow chart of the method for the manufacturingdual-leadframe multi-chip package in Embodiment 4.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiment 1: as shown in FIG. 3, a dual-leadframe multi-chip package,comprising two leadframes, two chips and two connecting plates. Twoleadframes are a first leadframe 101 and a second leadframe 102, whereinthe first leadframe 101 comprises a first die pad 110, multiple outerpins 111, 112, 113, 114 and multiple optional inner pins (not shown inthe figure). The multiple outer pins are used for the connection withthe internal chips correspondingly, and more or less pins may be adoptedduring real-life application; the second die pad 102 comprises a seconddie pad 120 and multiple optional inner pins (not shown in the figure)and multiple tie bars 121, 122. The tie bars 121, 122 are used forconnection between leadframes and fastening leadframes. Multiple chipseach has respectively a plurality of top contact areas (not shown in thefigure) and a bottom contact area (not shown in the figure)including afirst chip 130 and a second chip 140; the first chip 130 is mounted onthe first die pad 110 through bonding materials, preferably, throughconductive adhesive or soldering paste, and the second chip 140 ismounted on the second die pad 120 in the same manner through bondingmaterials; the bottom contact area of the first chip 130 is electricallyconnected with the first die pad 110, and the bottom contact area of thesecond chip 140 is electrically connected with the second die pad 120.Connecting plates are used for the connection in multi-chip package,wherein two connecting plates comprise a three-dimensional connectingplate 150 and a top connecting plate 160. The three-dimensionalconnecting plate 150 and the second die pad 120 form an integrated bodypreferably, or the three-dimensional connecting plate is electricallyconnected with the second die pad 120; and the three-dimensionalconnecting plate 150 connects a top contact area of the first chip 130by the conductive bonding materials, thus the first chip 130 iselectrically connected with the second die pad 120, and the second chip140 is electrically connected with the second die pad, so the first chip130 is electrically connected with the second chip 140 through thethree-dimensional connecting plate 150 and the second die pad 120. Thetop connecting plate 160 connects a top contact area of the second chip140 and the outer pin 114 of the first leadframe, preferably, the firstchip 130 is a high-side metal-oxide-semiconductor field effecttransistor, and the second chip 140 is a low-sidemetal-oxide-semiconductor field effect transistor. In this embodiment,the three-dimensional connecting plate 150 and the top connecting plate160, on one hand, reduces the distance between the high-sidemetal-oxide-semiconductor field effect transistor and the low-sidemetal-oxide-semiconductor field effect transistor, on the other hand,decreases the inductance and resistance between chips, wherein thethree-dimensional connecting plate 150 and the second die pad 120 areintegrated to ensure a stable connection between them (150 and 120). Theembodiment enumerates the package of two chips. In practical packaging,multiple chips can be set on the dual die pads. Through the connectionof connecting plate with various chips, the dual-leadframe multi-chippackaging is realized and the manufacturing process becomes simple andconvenient.

The manufacturing process of the dual-die pad multi-chip package, asshown in FIG. 4, comprising the following steps: first, provide a firstleadframe 101, wherein the first leadframe 101 comprises the first diepad 110, multiple outer pins 111, 112, 113, 114, and multiple optionalinner pins (not shown in the figure); and provide multiple chips,comprising the first chip 130 the second chip 140, preferably, the firstchip 130 is a high-side metal-oxide-semiconductor field effecttransistor, the second chip 140 is a low-side metal-oxide-semiconductorfield effect transistor, wherein the first chip 130 and the second chip140 each comprises a bottom contact area and a plurality of top contactareas respectively; second, the first chip 130 is mounted on the firstdie pad 110 through conductive bonding materials, the bottom contactarea of the first chip 130 is electrically connected with the first diepad, and led out through the outer pin 112 of the first leadframe; afterthat, provide a second leadframe 102 and a three-dimensional connectingplate 150, wherein the second die pad 102 comprises the second die pad120, multiple optional inner pins (not shown in the figure) and multipletie bars 121, 122, preferably, the second die pad 120 and thethree-dimensional connecting plate 150 form an integrated structure, orthe three-dimensional connecting plate 150 is electrically connectedwith the second die pad 120, the three-dimensional connecting plate 150connects the top contact area of the first chip 130 through conductivebonding material; afterwards, the second chip 140 is mounted on thesecond die pad 120 through conductive bonding materials, preferably,through conductive adhesive or soldering paste, the bottom contact areaof the second chip 140 is electrically connected with the second die pad120; in the end, provide a top connecting plate 160 connecting the topcontact area of the second chip 140 and an outer pin 114 of the firstleadframe 101 before encapsulation.

Embodiment 2: as shown in FIG. 5, a dual-leadframe multi-chip package,comprising two leadframes, three chips and two connecting plates. Twoleadframes are the first leadframe 201 and the second leadframe 202,wherein the first leadframe 201 comprises a first die pad 210, multipleouter pins 211, 212, 213, 214, 215 and multiple optional inner pins (notshown in the figure), multiple outer pins are used for connection withinternal chips correspondingly, and more or less pins can be adoptedduring real-life application; the second leadframe 202 comprises asecond die pad 220, multiple optional inner pins (not shown in thefigure) and multiple tie bars 221, 222 that are used for connectionbetween leadframes and fastening leadframes. Multiple chips haverespective top contact areas and bottom contact areas. The chipscomprise the first chip 230, the second chip 240 and the third chip 250;the first chip 230 and the third chip 250 are mounted on the first diepad 210 through conductive bonding materials, and the second chip 240 isset on the second die pad 220 through conductive bonding materials,preferably soldering paste or conductive adhesive as conductive bondingmaterials. The bottom contact areas of the first chip 230 and the thirdchip 250 are electrically connected with the outer pins 212, 213 of thefirst die pad 210, the bottom contact area of the second chip 240 iselectrically connected with the second die pad 220; the first chip 230and the second chip 240 further comprises top gate contact areas 2311,2411 different from the top contact areas, wherein the gate contactareas 2311, 2411 of the first chip 230 and the second chip 240 arerespectively connected with the outer pins 211, 214 of the first die pad210, preferably, the gate contact areas 2311, 2411 of the first chip 230and the second chip 240 are connected with the outer pins 211, 214 ofthe first leadframe 201 respectively through the bond wires 280. Twoconnecting plates include a three-dimensional connecting plate 260 and atop connecting plate 270 respectively, wherein the three-dimensionalconnecting plate 260 and the top connecting plate 270 are provided withmultiple holes 261, 271 on them, the multiple holes 261, 271 are usedfor adsorbing bonding materials so as to realize a stable connectionbetween the connecting plates and the top contact areas of chips.Preferably, the three-dimensional connecting plate 260 and the seconddie pad 220 form an integrated body, or the three-dimensional connectingplate 260 is electrically connected with the second die pad 220. Thethree-dimensional connecting plate 260 connects the top contact area ofthe first chip 230 so that the top contact area of the first chip 230 iselectrically connected with the second die pad 220; the top connectingplate 270 is used for connection in the multi-chip package, the topconnecting plate 270 connects the top contact area of the second chip220 and the outer pin 215 of the first die pad 210, and the topconnecting plate 270 also connects the top contact area of the thirdchip 250. Preferably, the first chip 230 is a high-sidemetal-oxide-semiconductor field effect transistor, the second chip 240is a low-side metal-oxide-semiconductor field effect transistor and thethird chip 250 is a bypass capacitor for decreasing parasiticinductance. In this embodiment, the three-dimensional connecting plate260 and the top connecting plate 270, on one hand, enable a shorterdistance between the high-side metal-oxide-semiconductor field effecttransistor and the low-side metal-oxide-semiconductor field effecttransistor, on the other hand, reduce the inductance and resistancebetween the chips, whereby the three-dimensional connecting plate 260 isstably connected with the second die pad 220 due to the integratedstructure of the three-dimensional connecting plate 260 and the seconddie pad 220. Moreover, the bypass capacitor reduces the parasiticinductance in circuit and improves the energy conversion efficiency ofthe whole device. The embodiment enumerates the package of two chips. Inpractical packaging, multiple chips can be mounted on the dualleadframes. Through the connection of connecting plates with variouschips, the dual-leadframe multi-chip packaging is realized.

The manufacturing process of the dual-leadframe multi-chip package, asshown in FIG. 6-10, comprises the following steps. As shown in FIG. 7,first, provide a first leadframe 201 comprising the first die pad 210,multiple outer pins 211, 212, 213, 214, 215 and multiple optional innerpins (not shown in the figure); second, provide multiple chips,comprising the first chip 230, the second chip 240 and the third chip250.

Preferably, the first chip 230 is a high-side metal-oxide-semiconductorfield effect transistor, the second chip 240 is a low-sidemetal-oxide-semiconductor field effect transistor and the third chip 250is a bypass capacitor, wherein the first chip 230, the second chip 240and the third chip 250 comprise the bottom contact areas (not shown inthe figure) and the top contact areas 231, 241, 251 respectively, asshown in FIG. 8, the first chip 230 and the third chip 250 are mountedon the first die pad 210. Preferably, the first chip 230 and the thirdchip 250 are mounted on the first die pad 210 through adhesive such asconductive adhesive or soldering paste, and meanwhile the bottom contactareas of the first chip 230 and the third chip 250 are electricallyconnected with the outer pins 212, 213 of the first die pad 210; third,as shown in FIG. 9, provide a second leadframe 202 and athree-dimensional connecting plate 260. Preferably, thethree-dimensional connecting plate 260 and the second die pad 220 forman integrated structure, or the three-dimensional connecting plate 260is electrically connected with the second die pad 220, wherein thesecond die pad 220 comprises multiple tie bars 221, 222. Thethree-dimensional connecting plate 260 is provided with multiple holes261 to adsorb adhesive at hole location. The three-dimensionalconnecting plate is connected with the top contact area 231 of the firstchip 230 through adhesive, preferably, the three-dimensional connectingplate 260 is connected with the source contact area of the first chip230 so that the top contact area of the first chip 230 is electricallyconnected with the second die pad 220. Afterwards, as shown in FIG. 10,the second chip 240 is mounted on the second die pad 220, and the secondchip 240 is electrically connected with the second die pad 220. A topconnecting plate 270 then provided with multiple holes 271 set on thetop connecting plate 270 to adsorb adhesive at the hole 271 locations soas for connecting the top connecting plate 270 to the top contact areaof the second chip, and the top connecting plate 270 connects the outerpin 215 of the first leadframe 201 and the top contact area 251 of thethird chip 250. After that, reflow soldering bead to form solder bumpson the gate contact areas 2311, 2411 of the first chip and the secondchip, and the gate contact areas 2311, 2411 of the first chip and thesecond chip are connected onto the pins 211, 214 of the first leadframethrough the bond wires 280. In the end, clean the leadframes and applyplastic molding for encapsulating the die pads, the connecting platesand the chips, such that only part of outer pins of the leadframes areexposed.

Embodiment 3: as shown in FIG. 11, a dual-leadframe multi-chip package,comprising two leadframes, two connecting plates and three chips,wherein the two leadframes are the first leadframe 301 and the secondleadframe 302 respectively, the two connecting plates are thethree-dimensional connecting plate 350 and the top connecting plate 360respectively, three chips are respectively the first chip, the secondchip 340 and the third chip, preferably, the first chip is a high-sidemetal-oxide-semiconductor field effect transistor, the second chip 340is a low-side metal-oxide-semiconductor field effect transistor and thethird chip is a bypass capacitor , as shown in FIG. 10, Embodiment 3 isbasically the same as Embodiment 2, the difference is that, thehigh-side metal-oxide-semiconductor field effect transistor and thebypass capacitor firstly integrate forming a chip 330 mounted on thefirst die pad 310. The integration of the high-sidemetal-oxide-semiconductor field effect transistor and the bypasscapacitor onto an integrated chip can reduce the parasitic inductance ofchips, improve the energy conversion efficiency of the whole device andraise the integration level of chip packaging.

Embodiment 4: as shown in FIG. 12, a dual-leadframe multi-chip package,comprising two leadframes, three chips and a connecting plate. Twoleadframes are respectively the first leadframe 401 and the secondleadframe 402. Preferably, the first leadframe and the second leadframeare two parts of an integrated base plate, wherein the integrated baseplate may comprise multiple parts, the first leadframe 401 comprises afirst die pad 410, multiple outer pins 411, 412, 413, 414, 415 andmultiple optional inner pins (not shown in the figure). The secondleadframe 402 comprises a second die pad 420, multiple optional innerpins (not shown in the figure) and multiple tie bars 421, 422. Themultiple chips each having a plurality of top contact areas and a bottomcontact area respectively, comprise a first chip 430, a second chip 440and a third chip 450. Preferably, the first chip 430 is a high-sidemetal-oxide-semiconductor field effect transistor, the second chip 440is a low-side metal-oxide-semiconductor field effect transistor and thethird chip 450 is a bypass capacitor. The first chip 430 and the thirdchip 450 are mounted on the first die pad 410 through conductive bondingmaterials, the second chip 440 is mounted on the second die pad 420through conductive bonding materials, the bottom contact areas of thefirst chip 430 and the third chip 450 are electrically connected withthe first die pad 410, the bottom contact area of the second chip 440 iselectrically connected with the second die pad 420, the first chip 430and the second chip 440 further comprise gate contact areas 4311, 4411,the gate contact areas 4311, 4411 of the first chip 430 and the secondchip 440 are further electrically connected with the outer pins 411, 414of the first leadframe 401. Preferably, the gate contact areas 4311,4411 of the first chip 430 and the second chip 440 are connected withthe outer pins 411, 414 of the first leadframe 401 through bond wires480 respectively. A top connecting plate 460 is provided with multipleholes 461 for adsorbing bonding materials so as to better connect thetop connecting plate 460 to the top contact areas. The top connectingplate 460 connects the top contact area of the second chip 440 and theouter pin 415 of the first leadframe 401. The plate 460 further connectsthe top contact area of the third chip 450. The top contact area 4312 ofthe first chip 430 is electrically connected with the second die pad 440through bond wires 470 so that the first chip 430 is electricallyconnected with the second chip 420. In this embodiment, the topconnecting plate 460 is used for connection between chips and betweenchips and the leadframes, thus to reduce the inductance between thechips, improve the stability of connection. The connection between thechips by means of bond wires provides the flexibility of chipconnection.

The manufacturing process of the dual-die pad multi-chip package,comprising the following steps, firstly, provide an integrated baseplate, wherein the integrated base plate comprises the first die pad 410and the second die pad 420 constituting an integrated leadframe of firstleadframe 401 and second leadframe 402. The first leadframe 401 furthercomprises multiple outer pin 411, 412, 413, 414, 415 and multipleoptional inner pins (not shown in the figure), the second leadframe 402further comprises multiple tie bars 421, 422.; afterwards, providemultiple chips, comprising the first chip 430, the second chip 440 andthe third chip 450. Preferably, the first chip 430 is a high-sidemetal-oxide-semiconductor field effect transistor, the second chip 440is a low-side metal-oxide-semiconductor field effect transistor and thethird chip 450 is a bypass capacitor. The first chip 430 and the thirdchip 450 are mounted on the first die pad 410.preferably throughadhesives such as conductive adhesive or soldering paste, and the bottomcontact areas of the first chip 430 and the third chip 450 areelectrically connected with the first die pad; secondarily, the topcontact area of the first chip 430 is connected with the second die padthrough bond wires 470. Afterwards, the second chip 440 is mounted onthe second die pad with its bottom contact area electrically connectedwith the second die pad 420; and then provide a top connecting plate460, wherein multiple holes 461 are set on the top connecting plate 460for adsorbing bonding materials, the top connecting plate 460 isconnected with a top contact area of the second chip 440 so that the topconnecting plate 460 connects the top contact area of the second chip440 and the outer pin 415 of the first leadframe 401, and the topconnecting plate 460 also connects a top contact area of the third chip450; afterwards, the gate contact areas 4311, 4411 of the first chip 430and the second chip 440 are connected with the pins 411, 414 of thefirst leadframe through the bond wires 480; in the end, clean theleadframes and package the die pads, the connecting plates and the chipsby means of plastic package such that only part of the outer pins of theleadframes are exposed.

It is necessary to recognize that the description above is theexplanation of the preferred embodiments and the present invention issubject to modification without deviating from the spirit and scopeclaimed by the claims attached.

The present invention is not limited to the abovementioned descriptionor details and methods displayed by the drawings. Other embodiments maybe also applicable for the present invention and multiple modes can beadopted. Moreover, we must be aware that the wording and terminology aswell as expression are for introducing the invention only, and shallnever be limited herein.

For this reason, it will be understood by a person skilled in this art,the concept on which the present invention is based can be applied todesign other structures, methods and systems for implementing severaltargets of the present invention. Therefore, it is very important thatthe claims are considered to include all equivalent conformations aslong as they are within the spirit and scope of the present invention.

1. A dual-leadframe multi-chip package comprises: a first leadframecomprising a first die pad and multiple outer pins, a second leadframecomprising a second die pad; a first chip mounted on the first die padwith a bottom contact area of the first chip electrically connected tothe first die pad, a second chip mounted on the second die pad with abottom contact area of the second chip electrically connected to thesecond die pad and a third chip mounted on the first die pad with abottom contact area of the third chip electrically connected to thefirst die pad; a top connecting plate electrically connecting a topcontact area of the second chip and a top contact area of the third chipto an outer pin; wherein a top contact area of the first chipelectrically connects to the second die pad.
 2. The dual-leadframemulti-chip package of claim 1 wherein: the top contact area of the firstchip electrically connects to the second die pad via bond wires.
 3. Thedual-leadframe multi-chip package of claim 1 wherein the first chip andthe third chip are integrated to form a chip mounted on the first diepad.
 4. The dual-leadframe multi-chip package of claim 1 wherein: thefirst chip is a high-side metal-oxide-semiconductor field effecttransistor, the second chip is a low-side metal-oxide-semiconductorfield effect transistor and the third chip is a bypass capacitor.